Deep trench isolation is commonly used in many bipolar and BiCMOS process technologies. It offers significant die size reduction over junction-isolated processes, as described in the following references: 1) Strachan et al, “A Trench-Isolated Power BiCMOS Process with Complementary High Performance Bipolars”, pp. 41-44, BCTM 2002; and 2) Parthasrathy et al, “A 0.25 um CMOS Based 70V Smart Power Technology with Deep Trench for High-Voltage Isolation”, pp. 459-462, IEDM, 2002, all incorporated herein by reference.
The trench is typically formed as a ring surrounding the entire transistor. FIG. 1 is a cross-sectional view of a prior art floating trench. The trench 10 is typically formed in silicon 11. The trench is lined with a thin liner oxide 12 and filled with polysilicon 14. The trench is sealed with field oxide (FOX) 16 on top. The trench 10 is always left electrically floating. The floating trench increases the breakdown voltage at the edge of the transistor by reducing field crowding at the edge, as described in U.S. Pat. No. 5,233,215 to Baliga and U.S. Pat. No. 6,246,101 to Akiyama. Both of these are field spreading techniques used only at the device edge or termination but not used in the active device region.